1. Field of the Invention
The present invention relates to the field of erasable programable logic devices and more specifically to data switching networks under the control of EPROM PALs.
2. The manufacture and use of electrically programmable read-only memories (EPROMs) are a well-known technology in the prior art. Recently, EPROM devices have been combined with programmable logic arrays (PLAs) and have provided a new advancement in the area of erasable programmable logic devices (EPLD). A typical EPLD array architecture is disclosed in two U.S. patents to Hartmann et al., U.S. Pat. Nos. 4,609,986 and 4,617,479. Such array architecture utilizes a plurality of EPROM cells which are arranged in a row and column matrix structure. Typically, output of the columns of an array are inputted into a macro architecture circuit for further dynamic processing of the outputs of the memory cells.
Also in the prior art, switching networks to transfer data from one communication line onto another communication line are well-known. Some of these switching networks incorporate drivers such that data on one line is transferred onto another line with the signal being boosted or amplified to provide the drive to transmit the signal onto the second line. In effect, a basic transceiver with a switching network for switching signals from one line to another is available in the prior art.
Although various forms of PLAs and transceiver/switching networks are known in the prior art, it is a different matter to combine the two technologies to provide a highly programmable and compact device which is economically implemented in a single semiconductor chip. By implementing an erasable programmable logic device to control a multi-port transceiver unit, a highly sophisticated data switching/transceiver unit is made to be controlled under control signals from the PLA. Further, by using PLAs, the signals from the transceiver unit can be fed back to the array to provide feedback signals for dynamic programming of the memory array. By implementing both structures as a combination, considerable space savings is possible and the complete unit can be economically implemented on a single semiconductor chip.
It is appreciated that what is needed is an improved device for manipulating signals onto various communication lines, wherein such manipulation is under the control of a dynamic programmable logic array.